Authors:
Hilmi Kayhan YILMAZ, Hakan ÇAYLAK, Serkan TOPALOĞLU
Publication:
2019 IEEE Asia-Pacific Microwave Conference (APMC), 51-53, 2019,
Abstract:
This paper presents an image reject downconverter design and implementation with improved image rejection for a broadband application without a filter bank. Moreover, the design includes Fractional-N PLL synthesizer implementation with mitigating N – boundary (fractional) spurs. An improvement technique was applied to the image reject downconverter design to improve insufficient image rejection ratios. This technique is based on adaptive amplitude compensation with respect to image frequency, which is obtained by increasing insertion loss of one of the mixers in the topology by applying DC voltage to the specified mixer. Thereby, enhanced image rejection ratios were attained. Besides, 40 dB spurious level rejection was obtained in the synthesizer design by the proposed spur reduction method which is based on a tunable reference frequency technique. Also, the proposed design is appropriate for FHSS systems due to synthesizer lock-up time.
Keywords:
Receivers, frequency conversion, phase locked loops, mixers, clocks, spread spectrum, radio frequency, phase noise