ABSTRACT
The LNA designed in this study operates in the 110-130 GHz bandwidth range, specifically designed for D-Band (110-170 GHz). The choice of D-Band aims to advance 6G transceiver technology. The process technology of this study is based on the 0.15-μm GaAs pHEMT process. Additionally, our literature search revealed no articles on the design of a D-Band RFIC LNA using this process. The selected 3-Stage Cascaded Cascode topology was determined due to its ability to deliver both high gain and broad bandwidth characteristics.
EM simulation and layout design of RFIC Low Noise Amplifier was performed on AWR Design Environment Software. As a result of the EM simulation of the designed LNA, 6.848 dB noise figure (NF) was obtained at the center frequency, and 17.56 - 26.55 dB gain was obtained in the bandwidth range. The total power consumption (PDC) of the circuit is 131.7 mW. The total chip area is 0.534 x 0.931 𝑚𝑚2.
Author
Batuhan PEKALP
Year
2024